1. Technical Field
The invention relates to the design of integrated circuits. More particularly, the invention relates to a method and apparatus for checking asynchronous circuit designs that are expressed using a hardware description language (HDL).
2. Description of the Prior Art
The bulk of application specific integrated circuits (ASICs) today are designed using a hardware description language (HDL), such as Verilog or VHDL. Designs that are coded with HDL are independent of specific ASIC suppliers, libraries, and tools. It is this independence that makes the designs portable and reusable. In many cases, the design may have various sub-components or modules that may be new or that have been used many times before in other designs. However, the various modules may not all operate in the same clock domain. For example, a storage element (e.g. a flip-flop) in one module may be clocked from a different source than a storage element in a second module. For instance, an embedded microprocessor may be clocked at 33 MHz inside an ASIC, and an interface component, such as a local area network (LAN) controller may be clocked at 10 MHz. If signals are passed from one module to the other, care must be taken to synchronize the signals from the source to the clock domain of the target. This is shown in FIG. 1, which is a block schematic diagram of a circuit that includes a synchronizer 20 for synchronizing signals between disparate circuit elements, e.g. a microprocessor 10 and a LAN controller 30.
Circuits that are not operated in synchronism are referred to as asynchronous circuits. While asynchronous circuits may be introduced into various designs intentionally, it is highly undesirable to produce a design that includes unplanned asynchronous circuits. Accordingly, if the synchronization of signals passing between clock domains is overlooked, timing problems in the form of setup or hold violations can occur, resulting in metastable conditions in flip-flops used in the design. This condition can cause various functional problems in a design, such as data corruption, or it may cause state machines to hang or transition to illegal states. In designs that have a large number of modules or components, there could be hundreds of signals that require synchronization. As such, the possibility of missing a signal that requires synchronization increases as the size of a design increases.
There are several known methods for insuring that a design is free of any unplanned asynchronous circuits. One method provides clearly defined interfaces between modules and makes the modules adhere to strict synchronization requirements. This technique requires a well understood and documented interface or the intimate knowledge by the designer of the design and all other designs that may interface with the design. This is a presently preferred design approach, but does have its failings. For example, this approach puts a premium on well documented specifications. If documentation is not prepared or neglected, the above approach is neither comprehensive nor complete.
Because of the increased capability of systems to integrate functions into ASIC's, circuit designs are becoming more complex and much larger. Design teams may consist of several designers and, therefore, intimate knowledge of all modules in a design may be difficult for any individual designer to attain. Because it is no longer common, nor practical, to have a single designer for an ASIC, knowledge of a design must be as portable as the design itself. If a designer is no longer available for consultation, the intimate knowledge of the design is lost and incorrect assumptions may be made about the design. This approach also does not lend itself well to the use of third party intellectual property that may be available for use in a larger design because knowledge of such third party intellectual property may no longer be available for design purposes.
Another approach for checking a design for asynchronous behavior provides a rigorous design review by designers to detect oversights in synchronization methods and practices. This approach is manual and labor intensive in nature, and is prone to error due to designer's lack of familiarity with a design.
A secondary factor in increasing the chance of error is the complexity of the design itself and the corresponding file structure associated with the design. As discussed above, ASIC designs can comprise hundreds of modules that tend to be arranged hierarchically. FIG. 2 is a block schematic diagram of an ASIC design showing the hierarchical arrangement of modules within the design. One fundamental problem with checking for asynchronous circuitry in a design is that a hierarchy forces additional complexity into the design. Tracking signals from a destination device at level 2 in branch A (level2a.v) to a source device at level 3 in branch B (not shown) requires a designer to scan many files, tracking both destination clock and data.
As the number of design layers and the depth of the hierarchy increase, the verification process becomes more problematic. The task is further complicated if the signal names of the clock or data change from one module to the next. For example, it is allowable (and in some cases necessary) in the HDL language to call a signal, e.g. CLK33 at one level and CLK in another level.
It would be advantageous to provide an improved method and apparatus for checking asynchronous HDL circuit designs.